1. Field of the Invention
The present invention generally relates to flash memory devices, and more particularly, to a method of forming flash memory cells and peripheral circuitry of flash memory devices having shallow trench isolation (STI) and flash memory devices produced thereby.
2. Discussion of the Related Art
Non-volatile memory devices, such as flash memory devices, may be provided in a NOR-type configuration or a NAND-type configuration. NAND-type nonvolatile semiconductor memory devices have a plurality of electrically rewritable nonvolatile memory cells connected in series together.
Two types of non-volatile memory cells are floating gate type memory cells and floating trap (charge trap) type memory cells. A floating gate type memory device may include a control gate and a conductive floating gate that is isolated, by an insulating layer, from a field effect transistor (FET) channel formed in a substrate. Floating gate type memory devices may be programmed by storing charges as free carriers on the conductive floating gate.
The multi-tunnel barrier of charge trap type is described in US Patent Nos. 20060198190, 20060202262, 20060202252, the disclosures of which are collectively, incorporated by reference herein. The multi-tunnel barrier of floating gate type is described in U.S. Pat. Nos. 6,784,484 and 7,026,686, the disclosures of which are collectively incorporated by reference herein.
Floating trap (charge trap) type memory devices may include a non-conductive charge storage layer between a gate electrode and a field effect transistor (FET) channel formed in a substrate. Floating trap type memory devices may be programmed by storing charges in traps in the non-conductive charge storage layer.
A floating gate type memory cell is similar to a standard MOSFET transistor, except that it has two gates instead of just one. One gate is the control gate (CG) like in other MOSFET transistors, but the second gate is a floating gate (FG) that is insulated all around by an oxide insulator. The floating gate (FG) is between the control gate (CG) and the substrate. Because the FG is isolated by its insulating oxide layer, any electrons placed on it get trapped there and thus store the information.
When electrons are trapped on the FG, they modify (partially cancel out) an electric field coming from the CG, which modifies the threshold voltage (Vt) of the cell. Thus, when the cell is “read” by placing a specific voltage on the control gate (CG), electrical current will either flow or not flow between the cell's source and drain connections, depending on the threshold voltage (Vt) of the cell. This presence or absence of current is sensed and translated into 1's and 0's, reproducing the stored data.
A conventional floating trap type unit memory device may include a SONOS (silicon-oxide-nitride-oxide-semiconductor) structure (layers). One very basic type of SONOS device may include a polycrystalline silicon (“polysilicon”, poly-Si) gate formed over a dielectric layer that includes a silicon nitride layer sandwiched between silicon oxide layers.
A floating trap type non-volatile memory device uses trap levels, such as those found in a silicon nitride layer, for memory operations. When a positive voltage is applied on the gate electrode, electrons are tunneled via the tunneling insulating layer to become trapped in the charge storage layer. As the electrons are accumulated in the charge storage layer, a threshold voltage of the memory device is increased, and the memory device becomes programmed. In contrast, when a negative voltage is applied to the gate electrode, trapped electrons are discharged to the semiconductor substrate via the tunneling insulating layer. Concurrently, holes become trapped by the tunneling insulating layer. Consequently, the threshold voltage of the unit memory device is decreased, and the memory device becomes erased.
Flash memory devices may have three types of transistors which are: the memory cell transistors (implementing nonvolatile data-storage memory cells); low voltage transistors; and high voltage transistors. Shallow trench isolation (STI), also known as ‘Box Isolation Technique’, is an integrated circuit feature that prevents electrical current leakage between adjacent semiconductor device components. STI is generally used on CMOS process technology nodes of 250 nanometers and smaller. STI is typically created early during the semiconductor device fabrication process, before transistors are formed. The key steps of the STI process involve etching a pattern of trenches in the silicon substrate, depositing one or more dielectric materials (such as silicon dioxide) to fill the trenches, and removing the excess dielectric material using a technique such as chemical-mechanical planarization (CMP).